Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, it relates to an interconnection circuit connected between two circuits.
FIG. 1 is a schematic diagram showing one example of a conventional interconnection circuit of a semiconductor integrated circuit for connecting two circuits.
Referring to FIG. 1, the interconnection circuit is connected between a first circuit 41 for applying an input signal and a second circuit 44 for outputting an output signal to the other circuit. An input terminal 8 and an output terminal 9 of the interconnection circuit are respectively connected to an output of the first circuit 41 and an output of the second circuit 44. The interconnection circuit comprises a parallel connection of four series circuits connected between the power supply V.sub.cc and the ground V.sub.ss. Although this interconnection circuit comprises an inverter as one example of an inner circuit 12, any logic circuit such as a flip-flop circuit or a latch circuit may be applied as another example of the inner circuit 12. The first series circuit comprises a series connection of junction diodes 5 and 6. The node of the diodes 5 and 6 is connected to the input terminal 8. The second series circuit comprises a series connection of a p channel MOS (Metal Oxide Semiconductor) field effect transistor 1 and an n channel MOS field effect transistor 2, namely, the first CMOS (Complementary MOS) inverter. The gates of the transistors 1 and 2 are connected together and a resistance 7 is connected between the node and the input terminal 8. The first and second series circuits constitute a preceding stage. The third series circuit comprises the inner circuit 12. The inner circuit 12 comprises a series connection of a p channel MOS field effect transistor 31 and an n channel MOS field effect transistor 32, namely, the second CMOS inverter. The gates of the transistors 31 and 32 are connected together to an output of the inverter of the preceding stage. The fourth series circuit comprises a series connection of a p channel MOS field effect transistor 3 and an n channel MOS field effect transistor 4, namely, the third CMOS inverter. The gates of the transistors 3 and 4 are connected together to an output of the inverter in the inner circuit 12. The output of this inverter constitutes an output terminal 9. The supply terminal 42 of the first circuit 41 is connected to a power supply V.sub.dd which is different from the power supply V.sub.cc and the ground terminal 43 is connected to the ground V.sub.ss. The supply terminal 45 of the second circuit 44 is connected to the power supply V.sub.dd and the ground terminal 46 is connected to the ground V.sub.ss. Therefore, the first and second circuits 41 and 44 operate even when the power supply V.sub.cc is off.
In the normal operation, an input signal applied from the first circuit 41 is applied to the input of the first inverter via the resistance 7. The input signal is inverted by the first, second and third inverters and the inverted input signal is outputted from the output terminal 9 as an output signal.
In general, the gate of the MOS field effect transistor is insulated from other portions by a dielectric such as SiO.sub.2 layer between the gate and a substrate. When a very high voltage is applied to the gate, the SiO.sub.2 layer is broken down by the high voltage and the transistor is destroyed. The break down voltage, which is determined dependent on the thickness of the SiO.sub.2 layer, is several ten volts in general. In order to prevent the break down of the SiO.sub.2 layer caused by the high voltage applied to the gate, usually an input protection circuit for protecting the MOS field effect transistor is provided.
The diodes 5 and 6 and the resistance 7 prevent the transistors 1 and 2 from being destroyed by the overvoltage, when an overvoltage is applied to the input terminal 8. In the following description, the voltage value of the power supply V.sub.cc is denoted by V.sub.cc, the voltage value of the ground V.sub.ss is denoted by V.sub.ss and the threshold voltage of the diodes 5 and 6 is denoted by V.sub.f.
When an overvoltage higher than V.sub.cc +V.sub.f is applied to the input terminal 8, the diode 5 conducts and clamps the input terminal 8 at the voltage of V.sub.cc +V.sub.f. Meanwhile, when an overvoltage lower than V.sub.ss -V.sub.f is applied to the input terminal 8, the diode 6 conducts and clamps the input terminal 8 at the voltage of V.sub.ss -V.sub.f. Therefore, when an overvoltage is applied to the input terminal 8, the diodes 5 and 6 bring the input terminal 8 to the voltage value of V.sub.cc +V.sub.f or to the value of V.sub.ss -V.sub.f, thereby preventing the destruction of the transistors 1 and 2 by the overvoltage.
The resistance 7 prevents the destruction of the transistors 1 and 2 by the overvoltage until the diode 5 or 6 conducts in response to the overvoltage applied to the input terminal 8. Namely, the resistance 7 is coupled together with a parasitic capacitance formed by the diodes 5 and 6 between one terminal of the resistance 7 and the power supply V.sub.cc or the ground V.sub.ss and with a parasitic capacitance formed by the transistors 1 and 2 between the other terminal of the resistance 7 and the power supply V.sub.ss or the ground V.sub.ss, thereby constituting a delay circuit. Therefore, when an overvoltage is applied to the input terminal 8, the delay circuit prevents the overvoltage from being immediately applied to the gates of the transistors 1 and 2. The diodes 5 and 6 conduct before the overvoltage reaches the gates of the transistors 1 and 2 and let the overvoltage go off through the diodes 5 or 6, so that the transistors 1 and 2 are protected from the destruction by the overvoltage.
FIG. 2 shows an equivalent circuit of the interconnection circuit shown in FIG. 1.
Compared with the circuit shown in FIG. 1, the equivalent circuit of FIG. 2 comprises parasitic diodes 22 and 23 which are equivalently connected in parallel to the transistors 3 and 4, respectively. The diodes 22 and 23 are formed due to the structure of the MOS field effect transistors 3 and 4.
FIG. 3 is a cross sectional view showing a model structure of an inverter including the MOS field effect transistors 3 and 4.
Referring to FIG. 3, the p type MOS transistor 3 comprises p.sup.+ type drain 53 and source 54 in an n.sup.- type substrate 50 and a gate 56 provided on a channel between the drain 53 and the source 54 with an insulating layer 52 of SiO.sub.2 interposed therebetween. The transistor 3 further comprises an n.sup.+ type region 55 for providing a substrate potential. A supply terminal 10 is connected to the source 54 and the region 55. The n type MOS transistor 4 comprises n.sup.+ type drain 59 and a source 58 in a p.sup.- type well 51 formed by diffusion in the n.sup.- type substrate 50 and a gate 60 provided on the channel between the drain 53 and a source 54 with an insulating layer 52 of SiO.sub.2 interposed therebetween. The transistor 4 further comprises a p.sup.+ type region 57 for providing the substrate potential. A ground terminal 11 is connected to the source 58 and the region 57. The gate 56 of the transistor 3 and the gate 60 of the transistor 4 are connected together to the output of the inner circuit 12 of the preceding stage, and the drain 53 of the transistor 3 and the drain 59 of the transistor 4 are connected together to constitute the output terminal 9.
In the inverter including the transistors 3 and 4 shown in FIG. 3, parasitic diodes 22 and 23 are formed due to the structure thereof. The parasitic diode 22 is formed between the drain 53 of the transistor 3 and the n.sup.- type substrate 50. The illustrated diode symbol 22 and the dotted line with an arrow show the path of the current flowing from the drain 53 toward the region 55. The parasitic diode 23 is formed between the drain 59 of the transistor 4 and the p.sup.- type well 51. The illustrated diode symbol 23 and the dotted line with an arrow show the path of the current flowing from the p.sup.- type well 51 toward the drain 59.
Again referring to FIGS. 1 and 2, malfunctions of the first circuit 41 and the second circuit 44 when the power supply V.sub.cc of this interconnection circuit is turned off will be described.
Referring to FIG. 1, when the power supply V.sub.cc of the interconnection circuit is turned off, the first circuit 41 is in operation and the output thereof is brought to the high level voltage, current flows from the output of the first circuit 41 to the interconnection circuit through the diode 5. This current flow causes a malfunction of the interconnection circuit. If the diodes 5 and 6 are omitted in order to prevent this problem, there arises another problem, namely, this circuit can not be protected from the input overvoltage.
Meanwhile, referring to FIG. 2, when the power supply V.sub.cc of the interconnection circuit is turned off and the second circuit 44 is in operation and the output thereof is brought to the high level voltage, a current flows from the output of the second circuit 44 to the interconnection circuit through the parasitic diode 22. This brings about another problem, namely, the current flow causes the malfunction of the interconnection circuit.
As a prior art of particular interest in relation to the present invention, a gate protection circuit employing an input clamp diode is disclosed in page 469 of "RCA Solid-State QMOS Data Book" published from RCA Corporation in 1985.